The present invention relates to the art of semiconductor fabrication and packaging.
Semiconductor chips commonly incorporate a large number of active electronic devices such as transistors and diodes, passive devices such as resistors and capacitors, and larger devices made up of combinations of such active and passive devices as, for example, logic gates, memory cells, amplifiers and the like, all formed within a single, integral body. Most commonly, the body is formed from silicon, although other materials such as diamond and compound semiconductors can be used. The active devices in the chip typically are provided in one or more layers extending parallel to the front and back surfaces of the chip.
The various electronic devices of the chip typically are interconnected with one another by metallic conductors such as traces extending within the chip in the horizontal or “x” and “y” direction and metallic vias extending in the vertical or “z” direction. Typically, the traces and vias are formed of conductive material deposited during fabrication of the chip as, for example, aluminum or polysilicon. The traces and vias used to interconnect the electronic elements of the chip with one another complicate design and fabrication of the chip.
The traces which are fabricated during manufacture of the chip do not always provide optimum electrical characteristics. For example, traces formed from aluminum have a relatively high resistivity. Although processes for fabricating traces in a chip from low-resistivity metals such as copper are known, these processes impose special requirements in chip fabrication. Further, even if a low-resistivity metal is employed, the size and hence the cross-sectional area of traces which can be accommodated within a chip are subject to severe limitations. Traces extending within a chip often follow indirect routes because other elements of the chip lie in a direct route between the electronic elements connected by the traces.
Additionally, chips must be connected to external circuit elements. In the conventional approach to chip packaging, each chip is incorporated in a separate package bearing leads or other external connecting elements. Contacts on the surface of the chip are connected to these external connecting elements. The external connecting elements on the package are connected to a conventional circuit board or other circuit-bearing substrate. Alternatively, several chips may be mounted in a single package, commonly referred to as a “multichip module.” These chips may be connected to one another and to a common set of external connecting elements, so that the entire assembly can be mounted to the substrate as a unit. In yet another alternative, the chip itself is attached directly to the substrate.
As described in Arima et al., U.S. Pat. No. 5,281,151, a rigid ceramic board may be provided with a set of “thin film” circuit layers overlying the ceramic board. The thin film layers include metallic traces on a material such as polyimide which has a relatively low dielectric constant. A chip is mounted to the thin film layers by solder balls in engagement with contacts on the chip. A signal can be routed from point to point within the chip along a signal path through a solder ball at one location on the chip, along a metallic trace of the thin film element and back into the chip through a solder ball at another location on the chip. The thin film layer assertedly provides low resistance and relatively rapid signal transmission between elements of the chip. In other embodiments, the interconnections can be formed within the ceramic circuit board itself, and the polyimide layers may be omitted.
Rostoker et al., U.S. Pat. Nos. 5,756,395 and 5,640,049 disclose generally similar interconnect structures associated with semiconductor chips. These devices rely on solder-bonding the interconnect structure to contacts on the active semiconductor chip itself. This in turn requires bulk melting of the solder during assembly, which in turn imposes significant constraints on the number and placement of the interconnects to provide sufficient space between interconnects and to avoid shorting between adjacent contacts.
Rai et al., U.S. Pat. No. 4,818,728 describes a process for making a composite semiconductor chip by use of projecting studs on one element received in pools of solder held in recesses on the surface of the opposing element, which suffers from similar drawbacks. The Rai et al. patent also mentions the use of a dielectric “bonding agent” on the surfaces of one semiconductor element to bond with the opposing element. Pace, U.S. Pat. No. 5,866,441 discloses the use of gold or similar ductile “protruberances” projecting from the surface of a chip which can be bonded to similar “protruberances” on a packaging module by processes such as thermocompression or ultrasonic bonding or by soldering. The resulting structure has a large gap between the chip and the module. To form a sealed structure, Pace uses a seal around the outside of the areas bearing the contacts. The horizontal dimensions of the chip and module must be increased to provide for this external seal, and the resulting structure contains a large air-filled gap.
As described in preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390, 5,518,964, 5,688,716 and International Publication Nos. WO 96/02068 and WO 97/11486, the disclosures of which are all incorporated by reference herein, it is desirable to provide interconnections between the contacts on a chip and external circuitry by providing a further dielectric element, which may be referred to as a “interposer” or “chip carrier” having terminals. Terminals on the dielectric element may be connected to the contacts on the chip by flexible leads. The terminals on the dielectric element may be connected to the substrate as, for example, by solder bonding the terminals to contact pads of the substrate. The dielectric element and terminals remain movable with respect to the chip so as to compensate for thermal expansion and contraction of the components. That is, various parts of the chip can move with respect to the terminals as the chip grows and shrinks during changes in temperature. In a particularly preferred arrangement, a compliant dielectric layer is provided as a separate component so that the compliant layer lies between the chip and the terminals. The compliant layer may be formed from a soft material such as a gel, elastomer, foam or the like. The compliant layer mechanically decouples the dielectric element and terminals from the chip and facilitates movement of the terminals relative to the chip. The compliant layer may also facilitate movement of the terminals in the Z direction, towards the chip, which further facilitates testing and mounting of the assembly.
As disclosed in International Publication No. WO 97/40958, the disclosure of which is also incorporated by reference herein, the electrically conductive parts on the dielectric element may be connected to the chip by masses of a fusible, electrically conductive material which is adapted to melt at temperatures encountered during processing or operation of the assembly. These masses may be constrained by a surrounding compliant dielectric material so that they remain coherent while in a molten state. The molten masses provide another form of deformable conductive element, which allows movement of the flexible dielectric element relative to chip. As further disclosed in commonly assigned patents and patent applications, one or more chips may be mounted to a common dielectric element or interposer, and additional circuit elements also may be connected to such a dielectric element. The dielectric element may incorporate conductive traces which form interconnections between the various chips and electronic components of the assembly.
As described in certain preferred embodiments of commonly assigned International Publication No. WO 98/44564, the disclosure of which is hereby incorporated by reference herein, an interposer which is movable with respect to the chip may itself provide interconnections between devices within a single chip. This provides a uniquely desirable solution in that it facilitates mounting of the chip to an external substrate and also facilitates connections between devices within the chip. In particularly preferred embodiments of the structures taught in the '486 International Application, the conductive paths within the interposer include multiple conductors and are connected to the chip by leads which also incorporate multiple conductors to provide controlled-impedance connections entire signal paths. This facilitates high-speed signal transmission.
Despite these and other improvements, still further methods and structures for semiconductor chip packaging would be desirable.